1. Field of the Invention
The present invention relates to memory devices and, more particularly, to writing data to and capturing data from Double Data Rate (DDR) memory devices.
2. Description of the Related Art
Double data rate (DDR) memory devices read and write data on both the positive and negative edges (transitions) of a clock signal. Thus, DDR memory provides twice the data rate of memory devices that only read and write data on the positive edge of a clock signal. Along with the increased bandwidth, a DDR memory substantially increases the complexity of the memory subsystem. Since two data words are now transferred every clock cycle as opposed to one in a single data rate device, the data eye, or window during which the data can reliably be captured, is significantly reduced. For example, FIG. 1A illustrates a clock signal and a data trace for a single data rate memory and a double data rate memory. As illustrated, the single data rate memory reads/writes one word per clock cycle while the double data rate device reads/writes two words per clock cycle. Thus, the data eye for data in a single data rate memory is much larger than the data eye for data from a double data rate memory. This aspect of the DDR design significantly increases the complexity of the timing considerations for reading and writing data to and from the DDR memory.
When data is written to a DDR memory, a write data strobe and the corresponding write data are sent to the DDR memory. The DDR memory uses the write data strobe to capture the write data so that it can be written to memory. The DDR memory assumes that the write data strobe is aligned with the data eye of the write data, therefore, the circuit interfacing with the DDR memory needs to output the write data strobe and the write data to the DDR memory with the appropriate timing relationship. The flight time for the write data and the associated write data strobe between the circuit and the DDR memory device should be equal to ensure proper timing when the signals reach the DDR memory.
To reduce complexity in the memory device, DDR memories typically require the write data strobe to arrive at the DDR memory within some percentage of the rising edge of the master clock for the DDR memory. For example, some DDR memory devices require the write data strobe to arrive at the DDR memory within ¼ of the rising edge of the DDR master clock. The write data strobe can be delayed to ensure that the write data strobe arrives at the DDR memory during the appropriate window. However, the amount of delay applied to the write data strobe depends on the distance the signal travels from the circuit to the DDR memory device. This distance is referred to as flight time. Since the flight time varies for different board designs, the DDR memory timing requirements require specialized circuitry to be developed for each new board design to ensure that the write data strobe and the write data arrive at the DDR memory with the appropriate timing relationship. This is inefficient and costly.
During a read operation, the circuit interfacing with the DDR memory receives read data along with a read data strobe from the DDR memory. As illustrated in FIG. 1B, the DDR memory sends the read data strobe coincident with the read data. In other words, the rising and falling edges 110 and 120 of the read data strobe occur when the read data is in transition. In order to reliably capture the read data, the read data strobe is delayed so that the rising and falling edges of the read data strobe are aligned with the data eye of the read data.
Since the read data strobe and the read data are coincident when sent from the DDR memory, it is assumed that the wires for the data and the associated read data strobe are routed with the same length between the DDR memory device and the receiving circuit. In other words, the receiving circuit assumes that the read data strobe and the read data are coincident when they are received. If they are not coincident, the delay applied by the circuit may not align the read data strobe with the center of the data eye of the read data. This may reduce the reliability of the read data capture.
The amount of delay applied to the read data strobe depends on the type of DDR memory device being used. The data eye during which the read data can be captured varies for different DDR memory devices. The relationship between the data strobe and the data sent from the DRAM devices is not always coincident. Each memory device may differ in the specification of this relationship. This can affect the optimum delay that should be applied to maximize the reliability of the data capture. Thus, the amount of delay that needs to be applied to the read data strobe varies for different DDR memory devices. Again, to meet these design requirements, the delay circuitry must often be redesigned for each type of DDR memory that is used in the memory subsystem.
Due to the high frequency nature of the double data rate transfers of data, what is needed are output cells positioned as close to the edge of the ASIC as possible to send data and control signals to the DDR memory. The output cells help to maintain the timing relationships between the data and corresponding control signals, thus increase the efficiency of writing data to the DDR memory.
What is also needed is a read data capture circuit that can be used to reliably capture read data.